Technical Field
The present invention generally relates to semiconductor devices, and more particularly to complementary metal oxide semiconductor (CMOS) devices and fabrication methods with capacitor fabrication integrated into the process.
Description of the Related Art
Complementary metal oxide semiconductor (CMOS) devices are continuously scaling down their size and device pitch. Gate pitch is also reduced in keeping with the decreasing scale. To accommodate the small gate pitch, patterning processes, such as, self-aligned double patterning (SADP) have been employed to provide the tight gate pitch patterning dimensions. However, the integration of capacitors and other peripheral devices cannot be easily integrated with the tight gate pitch employed for current CMOS devices.